(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of photoresist double coating to fabricate fine lines with narrower spacing than the resolution limit offered by the current best photolithography in the fabrication of integrated circuits.
(2) Description of the Prior Art
In the fabrication of integrated circuits, reductions in both the minimum line width and line spacing can lead to a denser circuit layout or smaller die size for the product. However, the minimum line width and line spacing on the wafer are limited conventionally by photolithography's resolution.
Referring to FIG. 1, there is shown a portion of a partially completed integrated circuit. A layer 12 which is to be etched is deposited over silicon substrate 10. Photoresist layer 14 coats the surface of the layer 12. As shown in FIG. 1, the photoresist layer 14 is patterned to create a photoresist mask. If the resolution of the photolithography process is R and the minimum misalignment tolerance between two layers is M, then the minimum pitch (line width (15)+line spacing (16)) is R+R=2R, by the conventional photolithographic process of the prior art.
U.S. Pat. No. 4,906,552 to Ngo et al describes a flood illumination patterning technique that achieves resolutions of 0.5 micrometers or less using a dual layer of photoresist. U.S. Pat. Nos. 5,091,290 to Rolfson, 4,704,347 to Vollenbroek et al, and 4,591,547 to Brownell all teach methods of dual layers of photoresist in which one layer of photoresist is at least partially over the other layer of photoresist.